gplcver - 2.12a-1.1+b2 main

Cver is a full 1995 IEEE P1364 standard Verilog simulator. It also
implements some of the 2001 P1364 standard features. All three
PLI interfaces (tf_, acc_, and vpi_) are implemented as defined
in the IEEE 2001 P1364 LRM.
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Homepage: http://www.pragmatic-c.com/gpl-cver