myhdl-cosimulation - 0.10-2 main

MyHDL turns Python into a hardware description and verification language,
providing hardware engineers with the power of the Python ecosystem.
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Python can then be used as an event-driven simulator using Python decorators
actively to specify what corresponds to 'processes' in Verilog / VHDL and
thereby achieve concurrency.
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This package provides the sources for executable extensions of the
core modules.