opensta-dev - 0~20191111gitc018cb2+dfsg-1.1 main

After synthesis, place and route of a digital circuit, it is necessary to
verify the timing of the design. OpenSTA is a tool for doing exactly that. It
has a Tcl interface for entering commands for analysing designs.
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It typically takes as input a verilog netlist, a liberty file, and other
parasitics information from the placed and routed design.
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This package contains the header files and some libraries for development.