Electric schematic editor
symbols needed for qelectrotech
examples files for qelectrotech
Flipper Zero firmware updater
Open-Source Digital Synthesis Flow
Technology files needed for qflow for osu018
Technology files needed for qflow for osu035
Technology files needed for qflow for osu050
Multi-level, over-the-cell maze router
tool to decode RFID tag data
external autorouter for pcb-rnd
In-System Programmer for 8051 MCUs using usbtiny
OBD-II vehicle diagnostic scanner
Small Device C Compiler
Small Device C Compiler (libraries)
Micro-controller simulator for SDCC
Logic analyzer and protocol decoder software suite (metapackage)
command-line frontend for the sigrok software
Firmware for Cypress FX2(LP) based logic analyzers
lean and mean AVR simulator
simple real time electronic circuit simulator
simulator for Microchip PIC16F84 microcontroller
Utilities for using the Wi-Spy USB spectrum analyzer hardware
MIPS R2000/R3000 emulator
OpenSource ST-Link tools replacement.
STM32 chip flashing utility using a serial bootloader
Simple command-line tool for LEGO Mindstorms NXT
Tcl/Tk based digital circuit editor and simulator
Tcl/Tk based digital circuit editor and simulator - data files
Tool to deliver firmware updates to TPM
USB hub per-port power control
Micro In-System Programmer for Atmel's AVR MCUs
USB HID relay driver
fast free Verilog simulator
Veroboard, Perfboard, and PCB layout and routing application
Veroboard, Perfboard, and PCB layout and routing application (data package)
tool for engraving PCBs using CNCs
Data logger for 1-Wire weather sensors
Data logger for 1-Wire weather sensors (MongoDB plugin)
Data logger for 1-Wire weather sensors (MySQL plugin)
Data logger for 1-Wire weather sensors (ODBC plugin)
Data logger for 1-Wire weather sensors (PostgreSQL plugin)
Data logger for 1-Wire weather sensors (SQLite plugin)
logic circuits simulator
JTAG flashing tool for FPGAs, CPLDs and EEPROMs
Draw circuit schematics or almost anything
schematic capture program
Framework for Verilog RTL synthesis
Framework for Verilog RTL synthesis (development files)